Legio X Fretensis : a prosopographical study of its officers, I-III c. A.D. / Edward Dabrowa

• Record Nr.: UNINA990004593740403321
• Autore: Dabrowa, Edward
• Pubbl/distr/stampa: Stuttgart : F. Steiner, 1993
• ISBN: 3-515-05809-5
• Descrizione fisica: 128 p. : ill. ; 24 cm
• Collana: Historia : Zeitschrift für Alte Geschichte , Einzelschriften ; 66
• Disciplina: 930; 355.00937
• Locazione: FLFBC; FGBC; DDR
• Collocazione: 355.009 DAB 1; XXI A 710 (66); DDR-XXIII Bb 175
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia

Gender and community : Muslim women's rights in India / / Vrinda Narain

• Record Nr.: UNINA9910819239503321
• Autore: Narain Vrinda <1965->
• Pubbl/distr/stampa: Toronto, [Ontario] ; ; Buffalo, [New York] ; ; London, [England] : , : University of Toronto Press, , 2001; ©2001
• ISBN: 1-282-03393-X; 9786612033933; 1-4426-7517-9
• Descrizione fisica: 1 online resource (213 p.)
• Disciplina: 346.540134
• Soggetti: Muslim women - Legal status, laws, etc - India; Women's rights - India; Islamic law - India; Electronic books.; Indien; India
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Bibliographic Level Mode of Issuance: Monograph
• Nota di bibliografia: Includes bibliographical references and index.
• Nota di contenuto: Contextualizing Muslim personal law -- Muslim personal law and the constitutional framework -- Naming the issues -- Negotiating the boundaries of gender and community : the role of the state.
• Sommario/riassunto: "In India, the legal status of Muslim women within the family is a topic of considerable controversy and debate. It is a complex issue that has implications for matters of not only gender equality, but also religious freedom, minority rights, and state policy regarding the accommodation of difference. Whereas the Constitution of India guarantees equality rights to all women, irrespective of religious affiliation, Muslim personal law, argues Vrinda Narain, explicitly discriminates on the basis of an individual's sex and religion." "Narain provides an analysis of the historical development and contemporary expression of Muslim personal law within a constitutional framework and examines the assertion that women's rights are a divisive force ; preventing the evolution of larger collective rights. She contends that an interrogation of the dominant religious ideology is necessary to prevent legislation from binding Muslim women to an essentialist notion of identity that denies them the possibility of challenging Muslim tradition. Combining feminist analysis and post-colonial and critical race theory with legal analysis, Gender and Community critically assesses issues of gender equality and minority rights within the larger social fabric. It offers a fresh look at the conceptualization of women as the markers of cultural community in Muslim India and advocates a perspective that seeks to unite the recognition of women's rights with respect for group integrity. These issues are significant not only for Muslim women in India, but also in the broader context of the accommodation of cultural diversity in pluralist democracies."--Jacket.

On-chip communication architectures : system on chip interconnect / / Sudeep Pasricha, Nikil Dutt

• Record Nr.: UNINA9911006627103321
• Autore: Pasricha Sudeep
• Pubbl/distr/stampa: Amsterdam ; ; Boston, : Elsevier / Morgan Kaufmann Publishers, c2008
• ISBN: 9786611370947; 9781281370945; 1281370940; 9780080558288; 0080558283
• Edizione: [1st edition]
• Descrizione fisica: 1 online resource (541 p.)
• Collana: Systems on Silicon
• Altri autori (Persone): DuttNikil
• Disciplina: 621.3815
• Soggetti: Systems on a chip; Microcomputers - Buses; Computer architecture; Interconnects (Integrated circuit technology)
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Description based upon print version of record.
• Nota di bibliografia: Includes bibliographical references and index.
• Nota di contenuto: Front Cover; On-Chip Communication Architectures: System on Chip ; Interconnect; Copyright Page; Contents; Preface; About the Authors; Acknowledgments; List of Contributors; CHAPTER 1 Introduction; 1.1. Trends in System-On-Chip Design; 1.2. Coping with Soc Design Complexity; 1.3. ESL Design Flow; 1.4. On-Chip Communication Architectures: A Quick Look; 1.5. Book Outline; CHAPTER 2 Basic Concepts of Bus-Based Communication Architectures; 2.1. Terminology; 2.2. Characteristics of Bus-Based Communication Architectures; 2.3. Data Transfer Modes; 2.4. Bus Topology Types; 2.5. Physical Implementation of Bus Wires2.6. Discussion: Buses in the DSM Era; 2.7. Summary; CHAPTER 3 On-Chip Communication Architecture Standards; 3.1. Standard On-Chip Bus-Based Communication Architectures; 3.2. Socket-Based On-Chip Bus Interface Standards; 3.3. Discussion: Off-Chip Bus Architecture Standards; 3.4. Summary; CHAPTER 4 Models for Performance Exploration; 4.1. Static Performance Estimation Models; 4.2. Dynamic (Simulation-Based) Performance Estimation Models; 4.3. Hybrid Communication Architecture Performance Estimation Approaches; 4.4. Summary; CHAPTER 5 Models for Power and Thermal Estimation5.1. Bus Wire Power Models; 5.2. Comprehensive Bus Architecture Power Models; 5.3. Bus Wire Thermal Models; 5.4. Discussion: PVT Variation-Aware Power Estimation; 5.5. Summary; CHAPTER 6 Synthesis of On-Chip Communication Architectures; 6.1. Bus Topology Synthesis; 6.2. Bus Protocol Parameter Synthesis; 6.3. Bus Topology and Protocol Parameter Synthesis; 6.4. Physical Implementation Aware Synthesis; 6.5. Memory-Communication Architecture Co-synthesis; 6.6. Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures; 6.7. SummaryCHAPTER 7 Encoding Techniques for On-Chip Communication Architectures; 7.1. Techniques for Power Reduction; 7.2. Techniques for Reducing Capacitive Crosstalk Delay; 7.3. Techniques for Reducing Power and Capacitive Crosstalk Effects; 7.4. Techniques for Reducing Inductive Crosstalk Effects; 7.5. Techniques for Fault Tolerance and Reliability; 7.6. Summary; CHAPTER 8 Custom Bus-Based On-Chip Communication Architecture Design; 8.1. Split Bus Architectures; 8.2. Serial Bus Architectures; 8.3. CDMA-Based Bus Architectures; 8.4. Asynchronous Bus Architectures; 8.5. Dynamically Reconfigurable Bus Architectures8.6. Summary; CHAPTER 9 On-Chip Communication Architecture Refinement and Interface Synthesis; 9.1. On-Chip Communication Architecture Refinement; 9.2. Interface Synthesis; 9.3. Discussion: Interface Synthesis; 9.4. Summary; CHAPTER 10 Verification and Security Issues in On-Chip Communication Architecture Design; 10.1. Verification of On-Chip Communication Protocols; 10.2. Compliance Verification for IP Block Integration; 10.3. Basic Concepts of SoC Security; 10.4. Security Support in Standard Bus Protocols; 10.5. Communication Architecture Enhancements for Improving SoC Security
• Sommario/riassunto: Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains