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1. |
Record Nr. |
UNINA990001653140403321 |
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Autore |
Piccioni, Antonio |
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Titolo |
L'ABC del diserbo / Antonio Piccioni |
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Pubbl/distr/stampa |
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Bologna : Edagricole, 1972 |
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Descrizione fisica |
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Collana |
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Universale Edagricole ; 78 |
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Disciplina |
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Locazione |
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Collocazione |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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2. |
Record Nr. |
UNISA996210087603316 |
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Autore |
Keehn Kelley <1975-> |
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Titolo |
She Inc [[electronic resource] ] : a woman's guide to maximizing her career potential / / Kelley Keehn |
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Pubbl/distr/stampa |
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Toronto [Ont.], : Insomniac Press, c2008 |
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ISBN |
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1-282-04690-X |
9786612046902 |
1-897415-32-X |
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Descrizione fisica |
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1 online resource (80 p.) |
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Disciplina |
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Soggetti |
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Career development |
Self-actualization (Psychology) in women |
Women - Vocational guidance |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Nota di contenuto |
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You Inc. -- Who's navigating your life? Developing "You Inc." -- Brand you -- The CEO called you -- Money doesn't buy happiness. Really? -- Finaancial basics for the savvy female CEO -- Understanding credit -- Conclusion. |
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Sommario/riassunto |
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Experts estimate that you will change not only your job, but your career an average of four to five times in your life. Stability and job security are things of the past. This book is suitable for employees, business owners, entrepreneurs, and those re-entering the work force. |
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3. |
Record Nr. |
UNINA9910299664003321 |
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Autore |
Alioto Massimo |
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Titolo |
Flip-Flop Design in Nanometer CMOS : From High Speed to Low Energy / / by Massimo Alioto, Elio Consoli, Gaetano Palumbo |
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Pubbl/distr/stampa |
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Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 |
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ISBN |
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Edizione |
[1st ed. 2015.] |
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Descrizione fisica |
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1 online resource (268 p.) |
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Disciplina |
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Soggetti |
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Electronic circuits |
Microprocessors |
Nanotechnology |
Circuits and Systems |
Electronic Circuits and Devices |
Processor Architectures |
Nanotechnology and Microengineering |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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The Logical Effort Method -- Design in the Energy-Delay Space -- Clocked Storage Elements -- Flip-Flop Optimized Design -- Analysis and Comparison in the Energy-Delay-Area Domain -- Energy Efficiency |
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Versus Clock Slope -- Hold Time Issues and Impact of variations on Flip-Flop Topologies -- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies. |
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Sommario/riassunto |
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This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate and postgraduate students (already familiar with digital circuits and timing). • Provides a unified treatment of Flip-Flop design and energy/variation-aware selection in nanometer CMOS VLSI systems • Offers in-depth analysis of the impact of nanometer effects on design tradeoffs • Presents a comprehensive analysis, by considering more than 20 topologies covering all relevant classes of circuits • Uses a rigorous framework based on novel methodologies to include layout parasitics within the circuit design loop . |
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